199 results on '"Chien Mo Li"'
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2. High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns.
3. Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis.
4. Diagnosis of Quantum Circuits in the NISQ Era.
5. Vmin Prediction Using Nondestructive Stress Test.
6. ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption.
7. Diagnosing Double Faulty Chains through Failing Bit Separation.
8. Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips.
9. Automatic Test Pattern Generation
10. Fault Modeling and Testing of Spiking Neural Network Chips.
11. Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning.
12. Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization.
13. Machine Learning-Based Test Pattern Generation for Neuromorphic Chips.
14. Diagnosis technique for Clustered Multiple Transition Delay Faults.
15. High Efficiency and Low Overkill Testing for Probabilistic Circuits.
16. qATG: Automatic Test Generation for Quantum Circuits.
17. Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips.
18. Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits.
19. ATPG and Test Compression for Probabilistic Circuits.
20. Test methodology for PCHB/PCFB Asynchronous Circuits.
21. Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction.
22. Parallel order ATPG for test compaction.
23. Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations.
24. DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG.
25. Physical-aware diagnosis of multiple interconnect defects.
26. Test Pattern Compression for Probabilistic Circuits.
27. Robust test pattern generation for hold-time faults in nanometer technologies.
28. A new method for parameter estimation of high-order polynomial-phase signals.
29. PSN-aware circuit test timing prediction using machine learning.
30. Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.
31. TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects.
32. A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse.
33. Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration.
34. Test Pattern Modification for Average IR-Drop Reduction.
35. Divide and conquer diagnosis for multiple defects.
36. Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.
37. Test Generation of Path Delay Faults Induced by Defects in Power TSV.
38. GPU-based n-detect transition fault ATPG.
39. Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor
40. 3D IC test scheduling using simulated annealing.
41. Test clock domain optimization for peak power supply noise reduction during scan.
42. An at-speed self-testable technique for the high speed domino adder.
43. An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects.
44. Static timing analysis for flexible TFT circuits.
45. CSER: BISER-based concurrent soft-error resilience.
46. Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics.
47. Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk.
48. Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits.
49. BIST design optimization for large-scale embedded memory cores.
50. Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits.
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